AI Chip Backend Design Engineer (5nm+), Singapore

WATT AI® PTE LTD () is an innovative high‑tech company co‑founded by hardware and software experts working on next‑gen AI processors and models from Silicon Valley. It is committed to developing high‑performance AI chips and computing clusters that support ultra‑large‑scale AI model training. We are looking to grow our team in Singapore.

You will be a member of an expert R&D team that enables static and dynamic transistor‑level analysis of the most advanced custom digital and mixed‑signal circuits built for AI markets.

• Enhancing and expanding the existing tools’ architecture to cover timing analysis.
• Creating new frameworks for analysis of effects dominant at 5 nm and below.
• Using machine learning technology to bring order‑of‑magnitude speed / capacity / usability improvements over existing solutions.
• Characterize the standard cell library for custom PVT base on foundry kit at 5 nm and below.

• A Master’s Degree in EE, CS, Math, Physics or related subjects, PhD preferred.
• Experience in EDA tools and one or more of transistor‑level timing, power, noise, aging, reliability, and EMIR analysis.
• Experience in development of circuit simulation or library characterization programs.
• High‑level understanding of SPICE simulation transistor models and gate‑level schematics.

• Proficiency in scripting languages (e.g., Tcl, Perl).

As a Back‑End IC Engineer you will apply the latest design methodology and milestone flow to deliver state‑of‑the‑art design over advanced technology node from RTL to GDSII. You should have very good experience in layout activities of block and level, including floor‑planning, partitioning, placement, clock tree synthesis, route and physical verification.

• Understanding of SoC for top‑down/bottom‑up physical design integration in advanced technologies.
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows.
• Must have knowledge of P&R, Extraction, Physical Verification, STA, ECO.
• Build automation flows wherever needed/adapt to existing flows for re‑use.

• A Master’s Degree in EE, CS, Math, Physics or related subjects, PhD preferred.
• A deep understanding of backend digital design flow.
• Proficient in timing constraints, physical constraints.
• Proficient in handling EDA tools across floorplan/partition/placement/CTS/route stages for SoC top‑level.
• Proficient with backend EDA tools Genus/Innovus/Quantus/Tempus, DC/Star‑RCXT/PrimeTime, PrimeRail/Voltus, Redhawk.

• Proficiency in scripting languages (e.g., Tcl, Perl).