SOC Physical Design Engineer, Toa Payoh

Responsibilities: . Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips. . Block owner, take block of 23 Million instances, working on Synthesis/APR(auto place and route)/Signoff . Block coordinator role for more than 510 blocks, solving the critical issue and give the solution to block owners. . TOP role for the complicated hierarchical chip (more than 20 Million instances plus 500+ macros), doing floorplan and partition, responsible for full chip tapeout
Requirements: . Bachelor/Master Degree in Electrical/Computer Engineer. . Experience in physical design with tape-outs. . Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC2 or Innovus. . Good in script programming with Perl, TCL/TK or other languages.